The present disclosure relates to data processing circuits, and in particular, to reducing power in a processor circuit.
A basic building block of data processors is the flip flop. A flip flop is an electronic circuit that may be in one of two states, corresponding to a binary 0 or 1. Thus, these circuits are used extensively in processors to store binary information. FIG. 1 shows a number flip flops 100-103 configured to receive N binary data values, D0-DN, store the binary values, and output the values, Q1-QN to another part of the circuit. As is typically the case, flip flops often receive new data values D0-DN at the same time in response to a trigger signal (e.g., a clock).
In data processing circuits, the use of flip flops to store data is ubiquitous. Modem processor circuits may include hundreds of thousands, millions, or tens of millions of flip flops. However, every time a flip flop changes state, wherein the output goes from low to high, the flip flop consumes power. Scaled across an entire processor, flip flops can consume a large amount of energy. This is particularly true in processors that use flip flops to perform intense data calculations, such as artificial intelligence processors, for example.
The present disclosure provides improved architectures for processors with reduced power consumption.